Description

The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single−ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device.

Features

• Maximum Frequency > 1.0 GHz Typical

• 50 ps Output−to−Output Skew

• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Synchronous Enable/Disable

• Master Reset for Synchronization of Multiple Chips

• VBB Output

• Pb−Free Packages are Available

MC100EP139DTR2属于集成电路（IC） > 时钟发生器，PLL，频率合成器。安森美半导体公司制造生产的MC100EP139DTR2时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。