MC100E175集成电路（IC）的锁存器规格书PDF中文资料

MC100E175属于集成电路（IC）的锁存器。由安森美半导体制造生产的MC100E175锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。

描述 Description

The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity), and using ODDPAR as the byte parity output.

The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.

特性 Features

• 9-Bit Latch

• Parity Detection/Generation

• 800 ps Max. D to Output

• Reset

• PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.5 V

• Internal Input 50 k Pulldown Resistors

• ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device MOdel; > 2 kV

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level:

Pb = 1

Pb−Free = 3

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34

• Transistor Count = 416 devices

• Pb−Free Packages are Available*