Description

The MC-45D32DC721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18 pieces of 128M DDR SDRAM: µPD45D128842 are assembled.

These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.

Decoupling capacitors are mounted on power supply line for noise reduction.

Features

• 33,554,432 words by 72 bits organization (ECC type)

• Clock frequency

• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge

• Double Data Rate interface

Differential CLK (/CLK) input

Data inputs and DM are synchronized with both edges of DQS

Data outputs and DQS are synchronized with a cross point of CLK and /CLK

• Quad internal banks operation

• Possible to assert random column address in every clock cycle

• Programmable Mode register set

/CAS latency (2, 2.5)

Burst length (2, 4, 8)

Wrap sequence (Sequential / Interleave)

• Automatic precharge and controlled precharge

• CBR (Auto) refresh and self refresh

• 2.5 V ± 0.2 V Power supply for VDD

• 2.5 V ± 0.2 V Power supply for VDDQ

• SSTL_2 compatible with all signals

• 4,096 refresh cycles / 64 ms

• Burst termination by Precharge command and Burst stop command

• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)

• Registered type

• Serial PD