MBM30LV0032-PFTN中文资料富士通数据手册PDF规格书

DESCRIPTION

The MBM30LV0032 device is a single 3.3 V 4M × 8 bit NAND flash memory organized as 528 byte × 16 pages × 512 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code(Specifications indicated are on condition that ECC system would be combined.). Program and read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page can be programmed in 200 µs and an 8K byte block can be erased in 2 ms under typical conditions.

FEATURES

• 3.3 V-only operating voltage (2.7 V to 3.6 V)

Minimizes system level power requirements

• Organization

Memory Cell Array : (4M + 128K) ×8 bit

Data Register : (512 + 16) ×8 bit

• Automatic Program and Erase

Page Program : (512 + 16) Byte

Block Erase : (8K + 256) Byte

• 528 Byte Page Read Operation

Random Access : 7 µs (Max.)

Serial Access : 35 ns (Max.)

• Fast Program and Erase

Program Time : 200 µs (Typ.) / page

Block Erase Time : 2 ms (Typ.) / block

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

• 1,000,000 write/erase cycle guaranteed (ECC system required)

• Command Register Operation

• Package

44(40)-pin TSOP Type II (0.8 mm pitch)

Normal/Reverse Type

• Data Retention: 10 years