MBM29F040C-55PFTR中文资料富士通数据手册PDF规格书

■ GENERAL DESCRIPTION

The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCCsupply. A 12.0 V VPPis not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

■ FEATURES

• Single 5.0 V read, program and erase Minimizes system level power requirements

• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs

• Compatible with JEDEC-standard byte-wide pinouts

32-pin PLCC (Package suffix: PD)

32-pin TSOP(I) (Package suffix: PF)

32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

• Minimum 100,000 write/erase cycles

• High performance

55 ns maximum access time

• Sector erase architecture

8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Embedded Erase™ Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program™ Algorithms

Automatically writes and verifies data at specified address

• DataPolling and Toggle Bit feature for detection of program or erase cycle completion

• Low VCCwrite inhibit ≤3.2 V

• Sector protection

Hardware method disables any combination of sectors from write or erase operations

• Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device