MBM29F033C-70PTR中文资料富士通数据手册PDF规格书

■ GENERAL DESCRIPTION

The MBM29F033C is a 32M-bit, 5.0 V-Only Flash memory organized as 4M bytes of 8 bits each. The 2M bytes of data is divided into 64 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29F033C is offered in a 40-pin TSOP package. This device is designed to be programmed in system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.

■ FEATURES

• Single 5.0 V read, write, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Pinout and software compatible with single-power supply Flash Superior inadvertent write protection

• 40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)

• Minimum 100,000 write/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

Uniform sectors of 64K bytes each Any combination of sectors can be erased. Also supports full chip erase

• Embedded EraseTM Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded ProgramTM Algorithms

Automatically programs and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/BUSY output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Low VCC write inhibit ≤ 3.2 V

• Hardware RESET pin Resets internal state machine to the read mode

• Erase Suspend/Resume

Supports reading or programming data to a sector not being erased

• Sector group protection

Hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 4 adjacent sectors of 64K bytes each)

• Temporary sector groups unprotection

Hardware method temporarily enable any combination of sectors from write or erase operations