MBM29DL321BD-12PBT中文资料32M (4M ×8/2M ×16) BIT Dual Operation数据手册Fujitsu规格书

描述 Description

■GENERAL DESCRIPTION
The MBM29DL32XTD/BD are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These
devices are designed to be programmed in-system with the standard system 3.0 V VCCsupply. 12.0 V VPPand
5.0 V VCCare not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.■FEATURES
• 0.33 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes (Refer to Table 1)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
   57-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   80 ns maximum access time
• Sector erase architecture
   Eight 4K word and sixty-three 32K word sectors in word mode
   Eight 8K byte and sixty-three 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Hidden ROM (Hi-ROM) region
   64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
   At VIH, allows removal of boot sector protection
   At VACC, increases program performance
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
•DataPolling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
•Low VCCwrite inhibit ≤2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESETpin.
• In accordance with CFI (Common Flash Memory Interface)

特性 Features

• 0.33 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
   Multiple devices available with different bank sizes (Refer to Table 1)
   Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
   Zero latency between read and write operations
   Read-while-erase
   Read-while-program
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
   57-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   80 ns maximum access time
• Sector erase architecture
   Eight 4K word and sixty-three 32K word sectors in word mode
   Eight 8K byte and sixty-three 64K byte sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Hidden ROM (Hi-ROM) region
   64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP/ACC input pin
   At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
   At VIH, allows removal of boot sector protection
   At VACC, increases program performance
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
•DataPolling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode.
•Low VCCwrite inhibit ≤2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESETpin.
• In accordance with CFI (Common Flash Memory Interface)