MB91F627PMC中文资料富士通数据手册PDF规格书

■ DESCRIPTION

The MB91625 series is a line of FUJITSU MICROELECTRONICS microcontrollers based on a 32-bit RISC CPU core that feature a variety of peripheral functions for embedded applications that demand high-performance and high-speed CPU processing.

This series is based on the FR80* family CPU and is implemented as a single chip.

* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.

■ FEATURES

• FR80 CPU

• 32-bit RISC, load/store architecture, five-stage pipeline

• General-purpose registers : 32-bit × 16

• 16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle

• Instructions suitable for embedded applications

- Memory-to-memory transfer, bit processing, barrel shift instructions, etc.

- Instruction support for high level languages

Function entry and exit instructions, instructions for register multi-load and multi-store

- Bit search instruction

“1” detection, “0” detection, transition point detection

- Branch instructions with delay slots

Reduced overhead when processing branches

- Register interlock functions

Facilitate coding in assembly language

- Built-in multiplier/instruction-level support

- Signed 32-bit multiplication : 5 cycles

- Signed 16-bit multiplication : 3 cycles

- Interrupts (save PC and PS) : 6 cycles, 16 priority levels

- Harvard architecture allowing program access and data access to be executed simultaneously

- Instruction prefetch function has been added with 4 word instruction queue of CPU

• Instruction compatible with FR family CPU

- Additional bit search instructions

- No resource instructions and coprocessor instructions

• Maximum operating frequency

• CPU : 60 MHz

• Resources : 40 MHz

• DMA controller (DMAC)

• 8 channels

• Address space : 32 bits (4 Gbytes)

• Transfer modes : Block transfer/burst transfer/demand transfer

• Address update : Increment/decrement/fixed (increment/decrement step size of 1, 2, or 4)

• Transfer data length : Selectable from 8-bit, 16-bit, 32-bit

• Block size : 1 to 16

• Number of transfers : 1 to 65535

• Transfer requests

- Requests from software

- Interrupt requests from peripheral resources (interrupt requests are shared, including external interrupts)

• Reload functions : Reload can be specified on all channels

• Priority order : Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...) or round-robin

• Interrupt requests : Interrupts can be generated for transfer complete, transfer error, and transfer interrupted.

• Multifunction serial interface

• 4 channels with 16-byte FIFO, 8 channels without FIFO

• Operation mode is selectable from the followings for each channel (For ch.0, I2C is not available.)

• UART

- Full-duplex double buffer

- Selectable parity on/off

- Built-in dedicated baud rate generator

- External clock can be used as a serial clock

- Error detection function for parity, frame and overrun errors

• CSIO

- Full-duplex double buffer

- Built-in dedicated baud rate generator

- Overrun error detection function

• I2C

- Supports both standard mode (Max 100 kbps)and Fast mode (Max 400 kbps)

- Some channels are 5 V tolerant

• Interrupts

• Total of 32 external interrupts (some pins are 5 V tolerant)

• Interrupts from peripheral resources

• Programmable interrupt levels (16 levels)

• Can be used to return from stop mode, sleep mode

• A/D converter

• 16 channels, 1 unit

• 10-bit resolution

• Conversion time : approx. 1.2 μs (PCLK = 33 MHz)

• Priority conversion (2 levels)

• Conversion modes : Single-shot conversion mode, scan conversion mode

• Activation sources : Software, external trigger, base timer

• Built-in FIFO for storing conversion data (for scan conversion:16, for priority conversion:4)

• D/A converter

• 2 channels

• 8-bit resolution (Continued)