MB91F211PMC-GSE1中文资料32-bit Proprietary Microcontroller数据手册Fujitsu规格书

描述 Description

■DESCRIPTIONS
MB91210 series is Fujitsu’s general-purpose 32-bit RISCmicrocontroller, which is designed for embedded control
applications that require high-speed real-time processing of consumer appliances. This microcontroller uses
FR60Lite as its CPU, compatible withother products in the FR* family.
This series incorporates a built-in LIN-UART and CAN controller.■FEATURES
•FR CPU
 
• 32-bit RISC, load/store architecture, 5-stage pipeline
 
• Maximum operating frequency : 40 MHz (Source oscillation is 4 MHz - PLL clock multiplier system)
 
• 16-bit fixed length instructions (basic instructions), one instruction per cycle
 
• Memory-memory transfer instructions, bit processing instructions, barrel shift instructions
    - Instructions adapted for embedded applications
 
• Function entry/exit instructions, multiple-register load/store instructions
    - Instructions supporting high-level language
 
• Register interlock function
    - Easier assembler coding enabled
 
• Built-in multiplier supported at the instruction level
    - Signed 32-bit multiplication: 5 cycles
    - Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction compatible with the FR family
•Internal ROM size & ROM type
 
• MASK ROM : 544 Kbytes (MB91213)
 
• Flash Memory : 288 Kbytes (MB91F211)
                        : 544 Kbytes (MB91F213)
•Internal RAM size : 24 Kbytes (MB91213/F213)
                        : 16 Kbytes (MB91F211)
•DMA Controller
 
• Capable of simultaneous operation of up to 5 channels
 
• Two transfer sources (internal peripheral/software)
•Bit Search Module (for REALOS)
 
• Search for the position of the first bit that changes from “1” to “0” in one word, from the MSB
•LIN-UART (7 channels)
 
• Asynchronous clock communication (start-stop synchronization), synchronous clock communication
 
• Synch-Break detection
 
• Dedicated built-in baud-rate generator for each channel
 
• SPI compliant (Mode 2 : clock synchronous communication mode)
•CAN Controller (3 channels)
 
• Maximum transfer rate : 1 Mbps
 
• 32 message buffer
•Timers
 
• 16-bit reload timer (3 channels) Selectable internal clock from 2/8/32 divisions
 
• 16-bit free-run timer (4 channels)
 
• Output compare (8 channels)
 
• Input capture (8 channels)
 
• 8/16-bit PPG (16 channels/8 channels) Selectable clock source from 1/2/16/64 division of peripheral clock
•Interrupt Controller
 
• Interrupts from internal peripherals
 
• Priority level can be set by software (16 levels)
•External Interrupt (16 channels)
 
• Selectable input from several pins
 
• Can be used as CAN WAKEUP
    Noise filter is inserted to CAN WAKEUP (Typ = 4 µs)
•A/D Converter (32 channels)
 
• 10-bit resolution
 
• Sequential comparison
    Conversion time : 3 µs
 
• Conversion modes (single conversion mode and scan conversion mode)
 
• Activation trigger (software/external trigger/peripheral interrupt)

特性 Features

•FR CPU
 
• 32-bit RISC, load/store architecture, 5-stage pipeline
 
• Maximum operating frequency : 40 MHz (Source oscillation is 4 MHz - PLL clock multiplier system)
 
• 16-bit fixed length instructions (basic instructions), one instruction per cycle
 
• Memory-memory transfer instructions, bit processing instructions, barrel shift instructions
    - Instructions adapted for embedded applications
 
• Function entry/exit instructions, multiple-register load/store instructions
    - Instructions supporting high-level language
 
• Register interlock function
    - Easier assembler coding enabled
 
• Built-in multiplier supported at the instruction level
    - Signed 32-bit multiplication: 5 cycles
    - Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction compatible with the FR family
•Internal ROM size & ROM type
 
• MASK ROM : 544 Kbytes (MB91213)
 
• Flash Memory : 288 Kbytes (MB91F211)
                        : 544 Kbytes (MB91F213)
•Internal RAM size : 24 Kbytes (MB91213/F213)
                        : 16 Kbytes (MB91F211)
•DMA Controller
 
• Capable of simultaneous operation of up to 5 channels
 
• Two transfer sources (internal peripheral/software)
•Bit Search Module (for REALOS)
 
• Search for the position of the first bit that changes from “1” to “0” in one word, from the MSB
•LIN-UART (7 channels)
 
• Asynchronous clock communication (start-stop synchronization), synchronous clock communication
 
• Synch-Break detection
 
• Dedicated built-in baud-rate generator for each channel
 
• SPI compliant (Mode 2 : clock synchronous communication mode)
•CAN Controller (3 channels)
 
• Maximum transfer rate : 1 Mbps
 
• 32 message buffer
•Timers
 
• 16-bit reload timer (3 channels) Selectable internal clock from 2/8/32 divisions
 
• 16-bit free-run timer (4 channels)
 
• Output compare (8 channels)
 
• Input capture (8 channels)
 
• 8/16-bit PPG (16 channels/8 channels) Selectable clock source from 1/2/16/64 division of peripheral clock
•Interrupt Controller
 
• Interrupts from internal peripherals
 
• Priority level can be set by software (16 levels)
•External Interrupt (16 channels)
 
• Selectable input from several pins
 
• Can be used as CAN WAKEUP
    Noise filter is inserted to CAN WAKEUP (Typ = 4 µs)
•A/D Converter (32 channels)
 
• 10-bit resolution
 
• Sequential comparison
    Conversion time : 3 µs
 
• Conversion modes (single conversion mode and scan conversion mode)
 
• Activation trigger (software/external trigger/peripheral interrupt)