MB91F155A中文资料富士通数据手册PDF规格书

■ DESCRIPTION

The MB91F155A/MB91155/MB91154 is a single-chip microcontroller using a RISC-CPU (FR 30 series) as its core. It contains peripheral I/O resources suitable for audio, MD and so on which are required to operate at low power consumption.

■ FEATURES

1. CPU

• 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline

• General-purpose registers : 32 bits × 16

• 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle

• Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications

• Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems supporting high level languages

• Register interlock functions, efficient assembly language description

• Branch instructions with delay slots : Reduced overhead time in branching executions

• Internal multiplier/supported at instruction level

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interrupt (PC and PS saving) : 6 cycles, 16 priority levels

2. Bus Interface

• 16-bit address output, 8/16-bit data input and output

• Basic bus cycle : 2-clock cycle

• Support for interface for various types of memory

• Unused data/address pins can be configured us input/output ports

• Support for little endian mode

3. Internal ROM

MB91F155A

FLASH products : 510 Kbytes

MB91155

Mask product : 510 Kbytes

MB91154

Mask product : 384 Kbytes

4. Internal RAM

Mask, FLASH products : 2 Kbytes

5. Internal Data RAM

MB91F155, MB91155

FLASH, Mask products : 32 Kbytes

MB91154

FLASH, Mask product : 20 Kbytes

6. DMAC

DMAC in descriptor format for placing transfer parameters on to the main memory.

Capable of transferring a maximum of eight internal and external factors combined.

Three channels for external factors

7. Bit Search Module

Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial I/O.

8. Timers

• 16-bit OCU × 8 channels, ICU × 4 channels, Free-run timer × 1 channel

• 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)

• 16-bit PPG timer × 6 channels. The output pulse cycle and duty can be varied as desired

• 16-bit reload timer × 4 channels

9. D/A Converter

• 8-bit × 3 channels

10. A/D Converter (Sequential Comparison Type)

• 10-bit × 8 channels

• Sequential conversion method (conversion time : 5.0 µs@33 MHz)

• Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode can be set respectively.

• Conversion starting function by hardware/software.

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