■DESCRIPTION

The FR family* is a line of single-chip microcontrollers based on the 32-bit high-performance RISC CPU while

integrating a variety of I/O resources for embedded control applications which require high-performance, high

speed CPU processing. The FR family contains multiple channels of data slicer and communication macros, best suited for embedded applications such as TV control.

■FEATURES

1. FR CPU

• 32-bit RISC, load/store architecture with a five-stage pipeline

• Operating frequency 33 MHz [PLL used : Oscillation frequency 16.5 MHz : Doubled]

• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle

• Instruction set optimized for embedded applications : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc.

• Instructions adapted for high-level languages : Functionentry/exit instructions, multiple-register load/store

instructions

• Register interlock functions : Facilitating coding in assemblers

• On-chip multiplier supported at the instruction level

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

• Harvard architecture allowing program accessand data access to be executed simultaneously

• Instruction prefetch feature added by a 4-word queue in the CPU

• Instruction set compatible with FR family

2. Simple External Bus interface

Capable of functioning 8-bit or 16-bit multiplex bus by setting with program

• Operating frequency : Max 16.5 MHz

• 8/16-bit data/address multiplex I/O

• Capable of chip-select signal output for completelyindependent four areas settable in 64 Kbytes minimum

• Basic bus cycle : 2 cycles

• Programmable automatic wait cycle generator capable of inserting wait cycles for each area

3. Internal Memory

MB91314A : 256 Kbytes Mask ROM, RAM 32 Kbytes

MB91F314 : 512 Kbytes Flash, RAM 32 Kbytes

4. DMAC (DMA Controller)

• 5 channels

• Two forwarding factors (internal peripheral/software)

• Addressing mode 20/24-bit address selection (increment/decrement/fixed)

• Transfer modes (burst transfer/step transfer/block transfer)

• Selectable transfer data size : 8, 16, or 32 bits

5. Bit Search Module (for REALOS)

Search for the position of the bit 1/0-changed first in one word from the MSB

6. Reload Timer (Including 1 Channel for REALOS)

• 16-bit timer ch.6

• The internal clock is optional from 2/8/32 division

7. Multi function Serial Interface

• 11 channels

• Full duplex double buffer

• Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication, clock synchronous communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max), high-speed mode (400 kbps Max)

• Parity on/off selectable

• Baud rate generator per channel

• Abundant error detection functions are provided (parity, frame, and overrun)

• External clock can be used as transfer clock

• Ch.0 to ch.2 correspond to DMA transfer.

• Ch.0 to ch.2 have a pair of 16 bytes FIFO buffers for transmission and reception.

• I2C bridge feature (among channels 0, 1, and 2)

• SPI mode

8. Interrupt Controller

• A total of 24 external interrupt lines (external interrupt pins INT23 to INT0)

• Interrupt from internal peripheral

• Programmable 16 priority levels

• Available for wakeup from STOP mode

9. A/D converter

• 10-bit resolution, 10 channels

• Successive approximation type : conversion time : About 8.0 µs

• Conversion mode (Single-shot conversion mode, scan conversion mode)

• Startup sources (software/external trigger)

10. PPG

• 4 channels

• 16-bit down counter, 16-bit data register with cycle setting buffer

• The internal clock is optional from 1/4/16/64 division

• Support for automatic cycle setting by DMA transfer

• Function for supporting remote control transmission

11. PWC

• 1 channel (1 input)

• 16-bit up counter

• Simple digital lowpass filter

12. Multi-function timer

• 4 channels

• Lowpass filter eliminating noise below a pre-set clock frequency

• Capable of pulse width measurement using seven types of clock signals

• Pin input event count function

• Interval timer function using seven types of clock signals and external input clock

• Internal HSYNC counter mode

13. Closed caption decoder feature

• 1 channel

• CC decoder function

• ID-1 (480i/480p) decoder function

14. Other interval timers

• Watch timer (32 kHz, Count up to 2 seconds)

• Watchdog timer

15. I/O port

Max 78 ports

16. Other features

• Internal oscillator circuit as a clock source

• INITis prepared as a reset terminal

• Watchdog timer reset and software reset are available

• Stop and sleep modes supported aslow-power consumption modes

• Gear function

• Built-in time base timer

• 5 V tolerant I/O (some pins)

• Package LQFP-120, 0.50 mm pitch, 16.0 mm ×16.0 mm

• CMOS technology (0.18µm)

• Power supply voltage 3.3 V ±0.3 V, 1.8 V ±0.15 V dual-power