MB91106PF数据手册Fujitsu中文资料规格书

描述 Description

■DESCRIPTION
The MB91106 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, instruction/data ROM of 64 Kbytes and RAM of 2 Kbytes are embedded in the MB91106. The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.■FEATURES
FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits ×16
• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions

特性 Features

FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
• General purpose registers: 32 bits ×16
• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions