MB90590数据手册Fujitsu中文资料规格书

描述 Description

■ DESCRIPTION
The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automo
tive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach.■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V)
• Instruction set to optimize controller applications
   Rich data types (bit, byte, word, long word)
   Rich addressing mode (23 types)
   Enhanced signed multiplication/division instruction and RETI instruction functions
   Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
   Adoption of system stack pointer
   Enhanced pointer indirect instructions
   Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
   Extended intelligent I/O service function (EI2OS) : Up to 10 channels
• Embedded ROM size and types
   Mask ROM : 256 Kbytes/384 Kbytes
   Flash ROM : 256 Kbytes/384 Kbytes
   Embedded RAM size : 6 Kbytes/8 Kbytes
• Flash ROM
   Supports automatic programming, Embedded Algorithm TM*
   Write/Erase/Erase-Suspend/Resume commands
   A flag indicating completion of the algorithm
   Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
   Erase can be performed on each block
   Block protection with external programming voltage
• Low-power consumption (stand-by) mode
   Sleep mode (mode in which CPU operating clock is stopped)
   Stop mode (mode in which oscillation is stopped)
   CPU intermittent operation mode
   Clock mode
   Hardware stand-by mode
• Process
   0.5µm CMOS technology
• I/O port
   General-purpose I/O ports : 78 ports
• Timer
   Watchdog timer : 1 channel
   8/16-bit PPG timer : 8/16-bit × 6 channels
   16-bit re-load timer : 2 channels

特性 Features

• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V)
• Instruction set to optimize controller applications
   Rich data types (bit, byte, word, long word)
   Rich addressing mode (23 types)
   Enhanced signed multiplication/division instruction and RETI instruction functions
   Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
   Adoption of system stack pointer
   Enhanced pointer indirect instructions
   Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
   Extended intelligent I/O service function (EI2OS) : Up to 10 channels
• Embedded ROM size and types
   Mask ROM : 256 Kbytes/384 Kbytes
   Flash ROM : 256 Kbytes/384 Kbytes
   Embedded RAM size : 6 Kbytes/8 Kbytes
• Flash ROM
   Supports automatic programming, Embedded Algorithm TM*
   Write/Erase/Erase-Suspend/Resume commands
   A flag indicating completion of the algorithm
   Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
   Erase can be performed on each block
   Block protection with external programming voltage
• Low-power consumption (stand-by) mode
   Sleep mode (mode in which CPU operating clock is stopped)
   Stop mode (mode in which oscillation is stopped)
   CPU intermittent operation mode
   Clock mode
   Hardware stand-by mode
• Process
   0.5µm CMOS technology
• I/O port
   General-purpose I/O ports : 78 ports
• Timer
   Watchdog timer : 1 channel
   8/16-bit PPG timer : 8/16-bit × 6 channels
   16-bit re-load timer : 2 channels