1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 页数：9 Pages

Maxim

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

文件：620.61 Kbytes 页数：10 Pages

Maxim

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 页数：9 Pages

Maxim

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

文件：620.61 Kbytes 页数：10 Pages

Maxim

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 页数：9 Pages

Maxim

美信