1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

General Description The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Features ♦ Impro

文件：120.43 Kbytes 页数：7 Pages

Maxim

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Package：8-TSSOP，8-MSOP（0.118"，3.00mm 宽）；包装：托盘 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:2 3GHZ 8UMAX

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亚德诺

Package：8-TSSOP，8-MSOP（0.118"，3.00mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:2 3GHZ 8UMAX

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亚德诺

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 页数：9 Pages

Maxim

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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

文件：620.61 Kbytes 页数：10 Pages

Maxim

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 页数：9 Pages

Maxim

美信