MAX3675数据手册ADI中文资料规格书

描述 Description

The MAX3675 is a complete clock-recovery and data-retiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply.
The MAX3675 has two differential input amplifiers: one accepts PECL levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated PLL.

特性 Features

• Single +3.3V or +5.0V Power Supply
• Complies with ANSI, ITU, and Bellcore SDH/SONET Specifications
• Low Power: 215mW at +3.3V
• Selectable Data Inputs, Differential PECL or Analog
• Received-Signal-Strength Indicator (RSSI)
• Loss-of-Power and Loss-of-Lock Monitors
• Differential PECL Clock and Data Outputs
• No External Reference Clock Required

应用 Application

• 上/下路复用器
• ATM交换
• 数字交叉连接
• SDH/SONET接入节点
• SDH/SONET传输系统