MAX3625A集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

General Description

The MAX3625A is a low-jitter, precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other networking applications.

Maxim’s proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment.

The MAX3625A has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies.

特性 Features

♦ Crystal Oscillator Interface: 24.8MHz to 27MHz

♦ CMOS Input: Up to 320MHz

♦ Output Frequencies

   Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz

   10G Fibre Channel: 159.375MHz, 318.75MHz

♦ Low Jitter

   0.14psRMS (1.875MHz to 20MHz)

   0.36psRMS (12kHz to 20MHz)

♦ Excellent Power-Supply Noise Rejection

♦ No External Loop Filter Capacitor Required

Applications

   Ethernet Networking Equipment

   Fibre Channel Storage Area Network