MACHLV210-15JC中文资料莱迪思数据手册PDF规格书

GENERAL DESCRIPTION

The MACHLV210 is a member of the high performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of I/O pull-up/pull-down resistors and low-voltage, low-power operation.

DISTINCTIVE CHARACTERISTICS

■ Low-voltage operation, 3.3-V JEDEC compatible — VCC = +3.0 V to +3.6 V

■ < 5 mA standby current

■ Patented design allows minimal standby current without speed degradation

■ Exclusively designed for 3.3-V applications

■ 44 Pins

■ 64 Macrocells

■ 12 ns tPDCommercial 18 ns tPDIndustrial

■ 83.3 MHz fCNT

■ 38 Bus-Friendly Inputs

■ 32 Outputs

■ 64 Flip-flops; 2 clock choices

■ 4 “PAL22V16” blocks with buried macrocells

■ Pin-, function-, and JEDEC-compatible with MACH210

■ Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215