M74HCT138TTR中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology.

If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED: tPD = 16ns (TYP.) at VCC = 4.5V

■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX)

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138