M68AW512DN70ZB1T中文资料意法半导体数据手册PDF规格书

SUMMARY DESCRIPTION

The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has a Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an automatic power-down feature, reducing the power consumption by over 99.

The M68AW512D is available in TFBGA48 (0.75 mm ball pitch) package.

FEATURES SUMMARY

■ SUPPLY VOLTAGE: 2.7 to 3.6V

■ 512K x 16 bits SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 55, 70ns

■ LOW STANDBY CURRENT

■ LOW VCC DATA RETENTION: 1.5V

■ TRI-STATE COMMON I/O

■ AUTOMATIC POWER DOWN