1Mbit 128K x8, 5V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply. This device

文件：373.32 Kbytes 页数：23 Pages

STMICROELECTRONICS

意法半导体

1Mbit 128K x8, 5V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply. This device

文件：373.32 Kbytes 页数：23 Pages

STMICROELECTRONICS

意法半导体

BGA

CHIPS

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BGA

SOURCE

索尔思光电

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