1152 x 8-BIT LINE MEMORY FIFO

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：145.77 Kbytes 页数：11 Pages

MITSUBISHI

三菱电机

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：2.19838 Mbytes 页数：12 Pages

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瑞萨

1152*8-BIT LINE MEMORY(FIFO)

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瑞萨

1152 x 8-BIT LINE MEMORY FIFO

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：145.77 Kbytes 页数：11 Pages

MITSUBISHI

三菱电机

1152*8-BIT LINE MEMORY(FIFO)

DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read and is most suitable as a buff

文件：2.19838 Mbytes 页数：12 Pages

RENESAS

瑞萨