M64811AGP中文资料三菱电机数据手册PDF规格书

DESCRIPTION

The M64811AGP is a 1.1GHz/500MHz band two-system one-chip PLL frequency synthesizer.

Using a high performance Bi-CMOS process , the product contains one two-modulus (1/32 and 1/33) prescaler that accepts inputs up to 1.1GHz and another two-modulus (1/16 and 1/17) prescaler that accepts inputs up to 500MHz ,thus helping make the equipment compact.

FEATURES

• Operating supply voltage : 2.7V~3.6V

• Operating temperature : -30°C~+85°C

• 2 PLL systems (1.1GHz and 500MHz) are on one chip .

PLL1 : 700MHz~1.1GHz PLL2 : 100MHz~500MHz

• Low power consumption (Icc=8mA Typ at Vcc=3V) .

• Dividing ratio setting ranges :

FIN1 for 1.1GHz VCO• • • • • N(VCO1)=1,024~131,071

FIN2 for 500MHz VCO• • • • • N(VCO2)=256~131,071

OSC for Fref • • • • • • • • • • • • • N(Fref)=5~2,047

• Each loop has input pin for sleep mode .

Power supplies to 2 loops can be independently turned ON/OFF .

Also can be controlled by the serial data . (When SLEEP1 and SLEEP2 is H . )

• The PLL standard oscillation circuit can adopt a B-E Colpitts type oscillation circuit to from a stable

oscillation circuit.

• Current controlled charge pump . (Icp=±2mA const.)

• Locked condition detecting output

If a phase difference smaller than 3 times (∆t) of the OSC period continues for 15 periods or

longer , the condition is judged as locked, and the LOCK terminal goes to L .

(When , for example , fosc=19.2 MHz , ∆t=156 ns)

• PLL lock/unlock status indicate function .

(Judged in the system turned on if the other system is turned off . )

• Small package (16pin SSOP, lead pitch : 0.65mm)

APPLICATION

• Digital cordless phone (CT2)

• Digital cellular phone (PDC)