M5M44800CJ中文资料三菱电机数据手册PDF规格书

DESCRIPTION

This is a family of 524288-word by 8-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential.

The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.

FEATURES

● Standard 28pin SOJ, 28pin TSOP (II)

● Single 5V±10 supply

● Low stand-by power dissipation

CMOS lnput level 5.5mW (Max)

CMOS Input level 550µW (Max) *

● Operating power dissipation

M5M44800Cxx-5,-5S 495mW (Max)

M5M44800Cxx-6,-6S 413mW (Max)

M5M44800Cxx-7,-7S 358mW (Max)

● Self refresh capability *

Self refresh current 150µA(Max)

● Extended refresh capability

Extended refresh current 150µA(Max)

● Fast page mode(1024-column random access),Read-modify-write,

RAS-only refresh, CAS before RAS refresh, Hidden refresh

capabilities.

● Early-write mode, CAS and OE to control output buffer impedance

● 1024 refresh cycles every 16.4ms (A0 ~A9)

● 1024 refresh cycles every 128ms (A0 ~A9) *

* :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S :option) only