M54HC113F1R中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The M54/74HC113 is a high speed CMOS DUAL JK FLIP FLOP WITH PRESET fabricated in silicon gate C2MOS technology.

■ HIGH SPEED

fMAX = 71 MHz (TYP.) at VCC = 5 V

■ LOW POWER DISSIPATION

ICC = 2 µA at TA = 25 °C

■ HIGH NOISE IMMUNITY

VNIH = VNIL = 28 VCC (MIN.)

■ OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

■ SYMMETRICAL OUTPUT IMPEDANCE

|IOH| = IOL = 4 mA (MIN.)

■ BALANCED PROPAGATION DELAYS

tPLH = tPHL

■ WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V to 6 V

■ PIN AND FUNCTION COMPATIBLE

WITH 54/74LS113