M393T5663AZ3-CD5中文资料三星数据手册PDF规格书

特性 Features

• JEDEC standard 1.8V ± 0.1V Power Supply

• VDDQ = 1.8V ± 0.1V

• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8 (Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination with selectable values(50/75/150 ohms or disable)

• PASR(Partial Array Self Refresh)

• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C

- support High Temperature Self-Refresh rate enable feature

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 68ball FBGA - 256Mx4/128Mx8, 56ball BGA - st.512Mbx4

• All of Lead-free products are compliant for RoHS