M32R中文资料瑞萨数据手册PDF规格书

Key Features

 RISC architecture

 32 -bit general purpose register x 16

 Number of instructions 83

 5 stage pipeline

 Two formats of 16 bit length instruction and 32 bit instruction are adopted

 The code size of the program can be suppressed by the instruction format of 16 bit

length

 MultiplyMultiply-accumulate function

 BuiltBuilt-in 32 32-bit x 16 16-bit multiplier enables execution of 32 32-bit x 32 32-bit integer

multiplication instruction with 3 CPUCLK

 Execute multiply multiply-accumulate instruction with 56 56-bit accumulator

 Peripheral circuit

 SRAM, cache, bus control circuit, interrupt controller, multifunction timer, serial I / O,

watchdog timer