M2V64S40BTP-6中文资料三菱电机数据手册PDF规格书

DESCRIPTION

M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3V ±0.3V power supply

- Max. Clock frequency -6 : 133MHz [PC133 ]

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 4096 refresh cycles /64ms

- LVTTL Interface

- Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch