M24C64-FMB5TPA中文资料意法半导体数据手册PDF规格书

特性 Features

■ Supports the I2C bus 100 kHz Standard-mode and 400 kHz Fast-mode

■ Single supply voltages (see Table 1 for root part numbers):

– 2.5 V to 5.5 V

– 1.8 V to 5.5 V

– 1.7 V to 5.5 V

■ Write Control input

■ Byte and Page Write

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

■ More than 1 Million write cycles

■ More than 40-year data retention

■ Packages

– ECOPACK® (RoHS compliant)

描述 Description

The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits and 16384 × 8 bits, respectively.

I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.