VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication rati

文件：391.61 Kbytes 页数：8 Pages

ICST

VCSO Based FEC Clock PLL

The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication ratios are pin-selected from Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-02\nLow phase jitter of 0.25 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz)\nPin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:\n255/238 (OTU1) Mapping and 238/;

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