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M2006-02A-669.3266中文资料VCSO BASED FEC CLOCK PLL数据手册Renesas规格书

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厂商型号

M2006-02A-669.3266

功能描述

VCSO BASED FEC CLOCK PLL

制造商

Renesas Renesas Technology Corp

中文名称

瑞萨 瑞萨科技有限公司

数据手册

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更新时间

2025-9-28 22:59:00

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M2006-02A-669.3266规格书详情

描述 Description

GENERAL DESCRIPTION
The M2006-02A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication ratios are pin-selected from pre-programming look-up tables.FEATURES
◆ Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-02
◆ Low phase jitter of 0.25 ps rms typical
   (12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
  
• 255/238 (OTU1) Mapping and 238/255 De-mapping
  
• 255/237 (OTU2) Mapping and 237/255 De-mapping
  
• 255/236 (OTU3) Mapping and 236/255 De-mapping
◆ Input reference and VCSO frequencies up to 700MHz, supports loop timing modes
   (Specify VCSO frequency at time of order)
◆ Supports active switching between inverse-FEC and non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation and for use with an unstable reference (i.e., similar to the M2006-12A - and pin-compatible - but without the Hitless Switching and Phase Build-out functions)
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package

特性 Features

◆ Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-02
◆ Low phase jitter of 0.25 ps rms typical
   (12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
  
• 255/238 (OTU1) Mapping and 238/255 De-mapping
  
• 255/237 (OTU2) Mapping and 237/255 De-mapping
  
• 255/236 (OTU3) Mapping and 236/255 De-mapping
◆ Input reference and VCSO frequencies up to 700MHz, supports loop timing modes
   (Specify VCSO frequency at time of order)
◆ Supports active switching between inverse-FEC and non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation and for use with an unstable reference (i.e., similar to the M2006-12A - and pin-compatible - but without the Hitless Switching and Phase Build-out functions)
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package

技术参数

  • 型号:

    M2006-02A-669.3266

  • 制造商:

    Integrated Device Technology Inc

  • 功能描述:

    9X9 LCC(LEAD FREE) - Bulk

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