GENERAL DESCRIPTION

The M031BT/M032BT series microcontroller (MCU) is based on Arm Cortex-M0 core with built-in Bluetooth Low Energy 5.0 (BLE 5.0) with rich peripherals and analog functions for applications that need wireless connectivity with multiple control functions. The M031BT/M032BT series is compliant with the BLE 5.0 standard supporting data rates up to 2 Mbps, offering 2.4 GHz proprietary stacks to achieve more possibility for wireless connectivity and Over-the-Air (OTA) for firmware upgrade. The M031BT/M032BT series solution allows those microcontroller applications to be the Internet of Things (IoT) devices with wireless connectivity.

The M031BT/M032BT series runs up to 72 MHz and features 64 Kbytes to 512 Kbytes Flash, 8 Kbytes to 96 Kbytes SRAM, 1.8V ~ 3.6V supply voltages, and supports 5V I/O tolerance within -40°C ~ 85°C operating temperature.

The M031BT/M032BT series provides a solution that need the connection with enhanced 2 MSPS fast conversion rate 12-bit ADC, 2 comparators and up to 24-ch 144 MHz PWM control. The M031BT/M032BT supports a fast and precise data conversion for the voltage, current, and sensor data, and fast response control to the external device. Additionally, the M031BT/M032BT series also provides plenty of peripherals including a Universal Serial Control Interface (USCI) that can be set as UART/SPI/I2C flexibly, 2 sets of I2C, up to 8 sets of UART, and 1-wire UART interface for data communication between master and slave devices. Moreover, part numbers with the M032BT series are all based on the M031BT series and enhanced with the crystal-less USB 2.0 full-speed device feature for USB related applications.

The M031BT series supports small form factor package QFN 48-pin (5 mm x 5 mm) that makes the PCB design to be compact size. The M032BT series offers QFN 68-pin (8 mm x 8 mm) for more functionality I/O control.

For the development, Nuvoton provides the NuMaker evaluation board and Nuvoton Nu-Link debugger. The 3rd Party IDE such as Keil MDK, IAR EWARM, Eclipse IDE with GNU GCC compilers are also supported.

M031BT/M032BT Features

Core and System

Arm® Cortex®-M0

 Arm® Cortex®-M0 processor, running up to 72 MHz

– 72 MHz at 2.0V-3.6V

– 48 MHz at 1.8V-3.6V

 Built-in Nested Vectored Interrupt Controller (NVIC)

 24-bit system tick timer

 Programmble and maskable interrupt

 Low Power Sleep mode by WFI and WFE instructions

Brown-out Detector (BOD)

 Two-level BOD with brown-out interrupt and reset option. (2.5V/2.0V)

Low Voltage Reset (LVR)

 LVR with 1.7V threshold voltage level.

Security

 96-bit Unique ID (UID).

 128-bit Unique Customer ID (UCID).

32-bit H/W Divider(HDIV)

 Signed (two’s complement) integer calculation

 32-bit dividend with 16-bit divisor calculation capacity

 32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit) Memories

Flash

 Dual bank 512 KB on-chip Application ROM (APROM) for Over-The-Air (OTA) upgrade.

 Up to 512 KB on-chip Application ROM (APROM).

 Up to 8 KB on-chip Flash for user-defined loader (LDROM)

 512 bytes execution-only Security Protection ROM (SPROM)

 All on-chip Flash support 512 bytes page erase

 Fast Flash programming verification with CRC-32 checksum calculation

 On-chip Flash programming with In-Chip Programming (ICP), In-System Programming (ISP) and In-Application Programming (IAP) capabilities

 2-wired ICP Flash updating through SWD/ICE interface SRAM

 Up to 96 KB on-chip SRAM

– 32 KB SRAM located in bank 0 that supports hardware parity check and retenion mode

– 32/32 KB SRAM located in bank 1 and bank 2

 Byte-, half-word- and word-access

 PDMA operation

Cyclic Redundancy Calculation (CRC)

 Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials

 Programmable initial value and seed value

 Programmable order reverse setting and one’s complement setting for input data and CRC checksum

 8-bit, 16-bit, and 32-bit data width

 8-bit write mode with 1-AHB clock cycle operation

 16-bit write mode with 2-AHB clock cycle operation

 32-bit write mode with 4-AHB clock cycle operation

 Uses DMA to write data with performing CRC operation

Peripheral DMA (PDMA)

 Up to 9 independent and configurable channels for automatic data transfer between memories and peripherals

 Basic and Scatter-Gather transfer modes

 Each channel supports circular buffer management using Scatter-Gather Transfer mode

 Fixed-priority and Round-robin priorities modes

 Single and burst transfer types

 Byte-, half-word- and word tranfer unit with count up to 65536

 Incremental or fixed source and destination address

Clocks

External Clock Source

 4~32 MHz High-speed eXternal crystal oscillator (HXT) for precise timing operation

 32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC function and low-power system operation

 16/32 MHz eXternal crystal oscillator(RF_XTAL) for RF transceiver

 Supports clock failure detection for external crystal oscillators and exception generatation (NMI)

Internal Clock Source

 48 MHz High-speed Internal RC oscillator (HIRC) dedicated for crystal-less USB.

 38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog timer and wakeup operation

 32 kHz low-power on-chip RC oscillator for RF transceiver with deviation less than ± 500 ppm

 Up to 144 MHz on-chip PLL, sourced from HIRC or HXT, allows CPU operation up to the maximim CPU frequency without the need for a high-frequency crystal

Real-Time Clock (RTC)

 The RTC clock source includes Low-speed external crystal oscillator (LXT)

 Able to wake up CPU from idle or power-down mode

 Supports ±5ppm within 5 seconds software clock accuracy compensation

 Supports Alarm registers (second, minute, hour, day, month, year)

 Supports RTC Time Tick and Alarm Match interrupt

 Automatic leap year recognition

 Supports 1 Hz clock output for calibration

Timers

32-bit Timer

 Up to 4 sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter from independent clock source

 One-shot, Periodic, Toggle and Continuous Counting operation modes

 Supports event counting function to count the event from external pins

 Supports external capture pin for interval measurement and resetting 24-bit up counter

 Supports chip wake-up function, if a timer interrupt signal is generated

PWM (PWM)

 Up to two PWM modules, each module provides three 16-bit counter and 6 output channels.

 Up to 12 independent input capture channels with 16-bit resolution counter

 Supports dead time with maximum divided 12-bit prescale

 Up, down or up-down PWM counter type

 Supports complementary mode for 3 complementary paired PWM output channels

 Counter synchronous start function

 Brake function with auto recovery mechanism

 Mask function and tri-state output for each PWM channel

 Able to trigger ADC to start conversion

Basic PWM (BPWM)

 Two 16-bit counters with 12-bit clock prescale for twelve 144 MHz PWM output channels.

 Up to 6 independent input capture channels with 16-bit resolution counter

 Up, down or up-down PWM counter type

 Counter synchronous start function

 Mask function and tri-state output for each PWM channel

 Able to trigger ADC to start conversion

Watchdog

 20-bit free running up counter for WDT time-out interval

 Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT with 9 selectable time-out period

 Able to wake up system from Power-down or Idle mode

 Time-out event to trigger interrupt or reset system

 Supports four WDT reset delay periods, including 1026, 130, 18 or 3 WDT_CLK reset delay period

 Configured to force WDT enabled on chip power-on or reset.

Window Watchdog

 Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit counter with 11-bit prescale

 Suspended in Idle/Power-down mode

Analog Interfaces

ADC

 Analog input voltage range: 0 ~ AVDD

 One 12-bit, 2 MSPS SAR ADC with up to 16 single-ended input channels or 8 differential input pairs; 10-bit accuracy is guaranteed.

 Internal channels for band-gap VBG input.

 Supports calibration capability.

 Four operation modes: Single mode, Burst mode, Single-cycle Scan mode and Continuous Scan mode.

 Analog-to-Digital conversion can be triggered by software enable (ADST), external pin (STADC), Timer 0~3 overflow pulse trigger, PWM trigger or BPWM trigger.

 Each conversion result is held in data register of each channel with valid and overrun indicators.

 Supports conversion result monitor by compare mode function.

 Configurable ADC external sampling time.

 PDMA operation.

 Supports floating detect function.

Analog Comparator (ACMP)

 Two Analog Comparators

 Supports three multiplexed I/O pins at positive input

 Supports I/O pins, band-gap, and 16-level Voltage divider from AVDD at negative input

 Supports wake up from Power-down by interrupt

 Supports triggers for brake events and cycle-by-cycle control for PWM

 Supports window compare mode and window latch mode

 Supports hysteresis function

 Supports calibration function

Radio

 Modem with Integrated RF Radio for 2.4 GHz Bluetooth communication link

 Compliant with Bluetooth 5 Low Energy Specification

 Supports proprietary 2.4 GHz protocols

 TX power: -20 to +8 dBm for M031BT series / +6 dBm for M032BT

series in BLE mode

 Rx Sensitivity: -94 dBm for M031BT series / -93 dBm for M032BT series (1 Mbps BLE mode)

 Immune to interference (image rejection, -25dBm)

 Data rate: 1Mbps and 2Mbps

 Integrated security: CRC, AES-128, AES-CCM for real-time processing of the data stream

 RSSI read-out

 Two power supply modes (DC-DC converter and LDO regulator) for RF transceiver

Communication Interfaces

Low-power UART

 Low-power UARTs with up to 7.2 MHz baud rate.

 Auto-Baud Rate measurement and baud rate compensation function.

 Supports low power UART (LPUART): baud rate clock from LXT (32.768 kHz) with 9600bps in Power-down mode even system clock is stopped.

 16-byte FIFOs with programmable level trigger

 Auto flow control (nCTS and nRTS)

 Supports IrDA (SIR) function

 Supports RS-485 9-bit mode and direction control

 Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function in idle mode.

 Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction

 Supports wake-up function

 8-bit receiver FIFO time-out detection function

 Supports break error, frame error, parity error and receive/transmit FIFO overflow detection function

 PDMA operation.

 Supports Single-wire function mode.

I2C

 Two sets of I2C devices with Master/Slave mode.

 Supports Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)

 Supports 7 bits mode

 Programmable clocks allowing for versatile rate control

 Supports multiple address recognition (four slave address with mask option)

 Supports multi-address power-down wake-up function

 PDMA operation

 I2C Port0 supports SMBus and PMBus

Quad SPI

 SPI Quad controller with Master/Slave mode.

 Up to 24 MHz in Master mode and up to 16 MHz in Slave mode at 1.8V~3.6V system voltage.

 Supports Dual and Quad I/O Transfer mode.

 Supports one data channel half-duplex transfer.

 Supports receive-only mode.

 Configurable bit length of a transfer word from 8 to 32-bit.

 Provides separate 8-level depth transmit and receive FIFO buffers.

 Supports MSB first or LSB first transfer sequence.

 Supports the byte reorder function.

 Supports Byte or Word Suspend mode.

 Supports 3-wired, no slave select signal, bi-direction interface.

 PDMA operation.

 Supports 2-bit Transfer mode.

SPI

 Dedicated SPI controller for RF transceiver.

 Up to 16 MHz at 1.8V~3.6V system voltage.

 Configurable bit length of a transfer word from 8 to 32-bit.

 Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers.

 MSB first or LSB first transfer sequence.

 Byte reorder function.

 Supports Byte or Word Suspend mode.

 Supports one data channel half-duplex transfer.

 Supports receive-only mode.

 PDMA operation.

Universal Serial Control Interface (USCI)

 Two sets of USCI, configured as UART, SPI or I2C function.

 Supports single byte TX and RX buffer mode UART

 Supports one transmit buffer and two receive buffers for data payload.

 Supports hardware auto flow control function and programmable flow control trigger level.

 9-bit Data Transfer.

 Baud rate detection by built-in capture event of baud rate generator.

 Supports wake-up function.

 PDMA operation.

SPI

 Supports Master or Slave mode operation.

 Supports one transmit buffer and two receive buffer for data payload.

 Configurable bit length of a transfer word from 4 to 16-bit.

 Supports MSB first or LSB first transfer sequence.

 Supports Word Suspend function.

 Supports 3-wire, no slave select signal, bi-direction interface.

 Supports wake-up function: input slave select transition.

 PDMA operation.

 Supports one data channel half-duplex transfer.

I2C

 Supports master and slave device capability.

 Supports one transmit buffer and two receive buffer for data payload.

 Communication in standard mode (100 kbps), fast mode (up to 400 kbps), and Fast mode plus (1 Mbps).

 Supports 7-bit mode (10-bit mode not supported).

 Supports 10-bit bus time out capability.

 Supports bus monitor mode.

 Supports power-down wake-up by data toggle or address match.

 Supports multiple address recognition.

 Supports device address flag.

 Programmable setup/hold time.

GPIO

 Supports four I/O modes: Quasi bi-direction, Push-Pull output, Open-Drain output and Input only with high impendence mode.

 Configured as interrupt source with edge/level trigger setting.

 I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode.

 Supports 5V-tolerance function except analog IO (PA.10, PA.11, PB.0~PB.15, PF.2~PF.5).

 Enabling the pin interrupt function will also enable the wake-up function.

 Input schmitt trigger function.

Advanced Connectivity

USB 2.0 Full Speed with on-chip

 Compliant with USB Revision 2.0 Specification.

 Supports suspend function when no bus activity existing for 3 ms.

transceiver

 8 configurable endpoints for configurable Isochronous, Bulk, Interrupt and Control transfer types.

 512 bytes configurable RAM for endpoint buffer.

 Remote wake-up capability.

 Supports Crystal-less function

 Start of Frame (SOF) locked clock pulse generation

 USB 2.0 link power management.