Adjustable Low Dropout Regulator

文件：157 Kbytes 页数：5 Pages

Microsemi

美高森美

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmi

文件：246.58 Kbytes 页数：18 Pages

Mitel

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

文件：491.07 Kbytes 页数：27 Pages

ZARLINK

Zarlink Semiconductor Inc

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmi

文件：246.58 Kbytes 页数：18 Pages

Mitel