LX24232中文资料LED Drivers数据手册Microchip规格书

描述 Description

LX24232 is a 32 channel display backlight LED controller, employed in Sony's 3D reference design. The device is part of a chipset consisting of LX24232 and LX23108 – an 8 channel LED driver. Each LX24232 controller is capable of controlling up to 32 LED channels, by controlling up to 4 LX23108 LED drivers. Each LX23108 8-channel LED driver contains eight FETs driving and controls up to 4x8 LED channels, where each channel is capable of driving a current of up to 200mA. LX24232 has 32 independent, frame-by-frame controlled PWM output channels; each output channel supports independent duty-cycle and phase delay control. LX24232 uses Vsync input for flexible synchronization schemes, including synchronization to either rising or falling edges, optimal Vsync jitter support, as well as single or multiple PWM cycles per frame support, and loss of Vsync support. LX24232 consists of an on-chip internal power supply control circuitry that can be used to adjust voltage level of an external LED power source. This is done by regulating LED supply voltage to optimum level, and thus minimizing system power loss. At the same time, accurate current regulation for each of the 32 LED strings is maintained. LX24232 includes an on-chip analog to digital converter for drain voltage (VD) measurements, for power supply control, fault detection and protection. LX24232 32-Channel Display Backlight LED Controller is configured through SPI interface which speeds up communication and reduces the number of control signals between LX24232 and host system (FPGA, Video Processor, and CPU). LX24232 supports a daisy chain connection in case more than 32 channels are required. LX24232 32-Channel Display Backlight LED Controller can detect three types of system faults on each of its 32 channels (over-temperature, open LEDs and short LEDs). After detecting faults, unit takes the required measures to protect system. LX24232 is capable of controlling up to 8 LX23108 drivers in a special configuration, where two consecutive channels are connected together for increased current support. For more details refer to application note.

特性 Features

·32 independent PWM output channels with independent 12-bit resolution duty-cycle (PWM high-time) control for each channel.
·Independent 12-bit phase delay (PD) control for each PWM output channel, optimized for 3D applications.
·32 independent, frame-by-frame controlled, Duty-Cycle data (DTC)
·32 independent, frame-by-frame controlled, Phase Delay data (PD)
·Duty-cycle & Phase Delay can be updated multiple times per frame
·Single or multiple PWM cycles in a single frame support.
·Frame-by-frame or multiple times per frame data rate through high-speed SPI interface
·Vsync synchronization.
·Configurable PWM output synchronization to either rising or falling edge of external sync pulse.
·Advanced Vsync jitter support
·Loss of Vsync support
·Optimized LED power supply voltage control.
·On-chip power supply trimming DAC for enhanced power supply control.
·±1.5% precision current matching.
·8-bit resolution current setting.
·Internal A/D for drain voltage measurements.
·Automatic minimum FET Vd report.
·Open string, short LED and over-temperature protection for each individual channel.
·On-chip thermal monitoring.
  ROHS, PB Free