丝印：LVE；Package：CP-16-22；2 A, Low VIN, Low Noise, CMOS Linear Regulator

FEATURES 2 A maximum output current Low input voltage supply range VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V Ultralow noise: 2 μV rms, 100 Hz to 100 kHz Noise spectra

文件：1.21309 Mbytes 页数：19 Pages

AD

亚德诺

丝印：LVEL11；Package：SOIC；3.3 V ECL 1:2 Fanout Buffer

1FEATURES · 1:2 ECL Fanout Buffer · Operating Range – PECL VCC = 3.0 V to 3.8 V With V EE = 0 V – NECL: VCC = 0 V with VEE = –3.0 to –3.8V · 5 ps Skew Between Outputs · Support for Clock Frequencies > 2.0 GHz · 265 ps Typical Propagation Delay · Deterministic Output Value for Open Input

文件：561.56 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL11；Package：SOIC；3.3 V ECL 1:2 Fanout Buffer

1FEATURES · 1:2 ECL Fanout Buffer · Operating Range – PECL VCC = 3.0 V to 3.8 V With V EE = 0 V – NECL: VCC = 0 V with VEE = –3.0 to –3.8V · 5 ps Skew Between Outputs · Support for Clock Frequencies > 2.0 GHz · 265 ps Typical Propagation Delay · Deterministic Output Value for Open Input

文件：561.56 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL11；Package：SOIC；3.3 V ECL 1:2 Fanout Buffer

1FEATURES · 1:2 ECL Fanout Buffer · Operating Range – PECL VCC = 3.0 V to 3.8 V With V EE = 0 V – NECL: VCC = 0 V with VEE = –3.0 to –3.8V · 5 ps Skew Between Outputs · Support for Clock Frequencies > 2.0 GHz · 265 ps Typical Propagation Delay · Deterministic Output Value for Open Input

文件：561.56 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEP11；Package：SOIC；2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer

1FEATURES · 1:2 PECL/ECL Fanout Buffer · Operating Range – PECL: VCC = 2.375 V to 3.8V With VEE = 0 V – NECL: VCC = 0 V With VEE = –2.375V to –3.8 V · Open Input Default State · Support for Clock Frequencies > 3.0 GHz · 240 ps Typical Propagation Delay · Deterministic Output Value for Ope

文件：563.47 Kbytes 页数：18 Pages

TI

德州仪器