丝印：LV165A；Package：WQFN；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SSOP；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SSOP；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器

丝印：LV165A；Package：TVSOP；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.35628 Mbytes 页数：44 Pages

TI

德州仪器