丝印：LV164A；Package：TSSOP；SN74LV164A 8-Bit Parallel-Out Serial Shift Registers

1 Features • VCC operation of 2 V to 5.5 V • Maximum tpd of 10.5 ns at 5 V • Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff supports live insertion, partial power-down mode, and back-driv

文件：2.01224 Mbytes 页数：36 Pages

TI

德州仪器

丝印：LV164A；Package：TSSOP；SN74LV164A 8-Bit Parallel-Out Serial Shift Registers

1 Features • VCC operation of 2 V to 5.5 V • Maximum tpd of 10.5 ns at 5 V • Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff supports live insertion, partial power-down mode, and back-drive

文件：2.13622 Mbytes 页数：35 Pages

TI

德州仪器

丝印：LV164A；Package：TSSOP；SN74LV164A 8-Bit Parallel-Out Serial Shift Registers

1 Features • VCC operation of 2 V to 5.5 V • Maximum tpd of 10.5 ns at 5 V • Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff supports live insertion, partial power-down mode, and back-driv

文件：2.01224 Mbytes 页数：36 Pages

TI

德州仪器

丝印：LV164A；Package：VQFN；SN74LV164A 8-Bit Parallel-Out Serial Shift Registers

1 Features • VCC operation of 2 V to 5.5 V • Maximum tpd of 10.5 ns at 5 V • Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff supports live insertion, partial power-down mode, and back-drive

文件：2.13622 Mbytes 页数：35 Pages

TI

德州仪器

丝印：LV164A；Package：VQFN；SN74LV164A 8-Bit Parallel-Out Serial Shift Registers

1 Features • VCC operation of 2 V to 5.5 V • Maximum tpd of 10.5 ns at 5 V • Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff supports live insertion, partial power-down mode, and back-driv

文件：2.01224 Mbytes 页数：36 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LV165A；Package：SOIC；SN74LV165A Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Increase the Number of Inputs on a Microcontr

文件：2.09571 Mbytes 页数：41 Pages

TI

德州仪器