| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
LS1021A | QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | |
LS1021A | TWR-LS1021A Reference Manual 文件：964.93 Kbytes 页数：71 Pages | FREESCALEFreescale Semiconductor, Inc 飞思卡尔飞思卡尔半导体 | FREESCALE | |
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP | ||
QorIQ LS1021A Data Sheet Features • Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture • LS1021A contains a dual-core Cortex-A7. Each core includes: – 32 KB L1 Instruction Cache (ECC protection) – 32 KB L1 Data Cache (ECC protection) – NEON co-processor – Floating Point (FPU) – QorIQ Trust Architecture and 文件：2.074489 Mbytes 页数：205 Pages | 恩XP | 恩XP |
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Freesca |
23+ |
FCPBGA5 |
8560 |
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6982 |
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- |
800 |
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- |
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FCPBGA-525(19x19) |
31500 |
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1820 |
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499 |
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20094 |
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BGA |
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