LPC47N267集成电路（IC）的专用规格书PDF中文资料

General Description

The SMSC LPC47N267 is a 3.3V PC 99 and ACPI 1.0 compliant Super I/O Controller. The LPC47N267 implements an LPC interface, a pin reduced ISA interface, for supported I/O and DMA cycles. In addition, this part includes an X-Bus interface that may be accessed through the LPC interface for supported I/O cycles (memory cycles are not supported by this device). The X-Bus interface supports as many as four external components and it offers three different modes of operation for interfacing with these components. The X-Bus interface has an added “Write Protect” feature that ensures that the Base Address and disable bit for each component can only be set by the BIOS to prevent corruption by any virus software. This part also includes 29 GPIO pins.

PRODUCT FEATURES

■ 3.3 Volt Operation (5V tolerant)

■ Programmable Wakeup Event Interface (IO_PME# Pin)

■ SMI Support (IO_SMI# Pin)

■ GPIOs (29)

■ Four IRQ Input Pins

■ X-Bus Interface

— Supports up to 4 external components

— Supports I/O cycles (No Memory Support)

— 8-Bit Data Transfer

— 6-Bit Address Qualification

— Write Protection for each component

■ XNOR Chain

■ PC99 and ACPI 1.0b Compliant

■ 100-pin STQFP Package

■ Intelligent Auto Power Management

■ 2.88MB Super I/O Floppy Disk Controller

— Licensed CMOS 765B Floppy Disk Controller

— Software and Register Compatible with SMSCs Proprietary 82077AA Compatible Core

— Supports One Floppy Drive Directly

— Configurable Open Drain/Push-Pull Output Drivers

— Supports Vertical Recording Format

— 16-Byte Data FIFO

— 100 IBM Compatibility

— Detects All Overrun and Underrun Conditions

— Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

— DMA Enable Logic

— Data Rate and Drive Control Registers

— Swap Drives A and B

— Non-Burst Mode DMA Option

— 48 Base I/O Address, 15 IRQ and 3 DMA Options

— Forceable Write Protect and Disk Change Controls

■ Floppy Disk Available on Parallel Port Pins (ACPI Compliant)

■ Enhanced Digital Data Separator

— 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

— Programmable Precompensation Modes

■ Serial Ports

— Two Full Function Serial Ports

— High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs

— Supports 230k and 460k Baud

— Programmable Baud Rate Generator

— Modem Control Circuitry

■ Infrared Communications Controller

— IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support

— 2 IR Ports

— 96 Base I/O Address, 15 IRQ Options and 3 DMA Options

■ Multi-Mode Parallel Port with ChiProtect

— Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port

— Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

— IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

— ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On

— 192 Base I/O Address, 15 IRQ and 3 DMA Options

■ LPC Bus Host Interface

— Multiplexed Command, Address and Data Bus

— 8-Bit I/O Transfers

— 8-Bit DMA Transfers

— 16-Bit Address Qualification

— Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems

— PCI nCLKRUN Support

— Power Management Event (IO_PME#) Interface Pin

■ Mechanical Package

— 100 pin STQFP (12mm x 12mm body size)