LPC2194HBD64数据手册恩XP中文资料规格书

描述 Description

The LPC2194 is based on a 16/32-bit Arm7TDMI-S™ CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
With its compact 64-pin package, low power consumption, various 32-bit timers, 4-channel 10-bit ADC, four advanced CAN channels, PWM channels and 46 fast GPIO lines with up to nine external interrupt pins this microcontroller is particularly suitable for automotive applications such as a CAN gateway that connects several CAN busses or a CAN bridge between sub networks at different speeds. Sensors with CAN interface or debugging via CAN are additional applications that need more than two CAN interfaces. It is also an adequate solution for industrial control, medical systems and fault-tolerant maintenance buses. With a wide range of additional serial communications interfaces, it is also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2194 will apply to devices with and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate from other devices only when necessary.

特性 Features

2.1 Key features brought by LPC2194/01 devices
• Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device. They also allow for a port pin to be read at any time regardless of its function.
• Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are 5 V tolerant when configured for digital I/O function(s).
• UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware.
• Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
• SPI programmable data length and master mode enhancement.
• Diversified Code Read Protection (CRP) enables different security levels to be implemented. This feature is available in LPC2194/00 devices as well.
• General purpose timers can operate as external event counters.
2.2 Key features common for all devices
• 16/32-bit Arm7TDMI-S™ microcontroller in a tiny LQFP64 package.
• 16 kB on-chip SRAM and 256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation.
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms.
• EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software as well as high speed real-time tracing of instruction execution.
• Four interconnected CAN interfaces with advanced acceptance filters. Additional serial interfaces are two UARTs (16C550), Fast I²C-bus (400 kbit/s) and two SPIs.
• Four channel 10-bit ADC with conversion time as low as 2.44 µs.
• Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock and Watchdog.
• Vectored Interrupt Controller with configurable priorities and vector addresses.
• Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive external interrupt pins available.
• Operating temperature range from -40 °C to +125 °C.
• 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop with settling time of 100 µs.
• On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
• Two low power modes, Idle and Power-down.
• Processor wake-up from Power-down mode via external interrupt.
• Individual enable/disable of peripheral functions for power optimization.
• Dual power supply:
• CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
• I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.