LPC11U24FBD64/401中文资料恩XP数据手册PDF规格书

description

The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11U2x operate at CPU frequencies of up to 50 MHz.

Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the

LPC11U2x brings unparalleled design flexibility and seamless integration to today’s

demanding connectivity solutions.

The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to

10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC

(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.

For additional documentation related to the LPC11U2x parts, see Section 15

“References”.

Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 32 kB on-chip flash program memory.

 Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

 Up to 10 kB SRAM data memory.

 16 kB boot ROM.

 In-System Programming (ISP) and In-Application Programming (IAP) for flash and

EEPROM via on-chip bootloader software.

 ROM-based USB drivers. Flash updates via USB supported.

 ROM-based 32-bit integer division routines.

 Debug options:

 Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan

Description Language).

 Serial Wire Debug.

 Digital peripherals:

 Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

 Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.

 Two GPIO grouped interrupt modules enable an interrupt based on a

programmable pattern of input states of a group of GPIO pins.

 High-current source output driver (20 mA) on one pin.

 High-current sink driver (20 mA) on true open-drain pins.

 Four general-purpose counter/timers with a total of up to 5 capture inputs and 13

match outputs.

 Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal

low-power WatchDog Oscillator (WDO).

 Analog peripherals:

 10-bit ADC with input multiplexing among eight pins.

 Serial interfaces:

 USB 2.0 full-speed device controller.

 USART (Universal Synchronous Asynchronous Receiver/Transmitter) with

fractional baud rate generation, internal FIFO, a full modem control handshake

interface, and support for RS-485/9-bit mode and synchronous mode. USART

supports an asynchronous smart card interface (ISO 7816-3).

 Two SSP (Synchronous Serial Port) controllers with FIFO and multi-protocol

capabilities.

 I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with

a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.

 Clock generation:

 Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).

 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as

a system clock.

 Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable

frequency output.

 PLL allows CPU operation up to the maximum CPU rate with the system oscillator

or the IRC as clock sources.

 A second, dedicated PLL is provided for USB.

 Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, Power-down, and Deep power-down modes.

 Power profiles residing in boot ROM provide optimized performance and minimized

power consumption for any given application through one simple function call.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

 Processor wake-up from Deep-sleep and Power-down modes via reset, selectable

GPIO pins, watchdog interrupt, or USB port activity.

 Processor wake-up from Deep power-down mode using one special function pin.

 Power-On Reset (POR).

 Brownout detect with four separate thresholds for interrupt and forced reset.

 Unique device serial number for identification.

 Single 3.3 V power supply (1.8 V to 3.6 V).

 Temperature range 40 C to +85 C.

 Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages.

Applications

 Consumer peripherals  Handheld scanners

 Medical  USB audio devices

 Industrial control