LPC1104UK中文资料恩XP数据手册PDF规格书

General description

The LPC1102/1104 are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC1102/1104 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1102/1104 includes 32 kB of flash memory, 8 kB of

data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four

general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

Remark: The LPC1104 has a revised pinout and contains several features not found in

the LPC1102:

• Two extra GPIO pins (PIO0_1 and PIO0_6).

• Extra match output (CT32B0_MAT2).

• CLKOUT feature.

• Easier re-entry to ISP via PIO0_1.

• SSP0_CLK available on two pins (A1 and A2) to support debugging of SSP

communication.

• Better positioning of the XTALIN pin for easier PCB layout.

Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Serial Wire Debug.

 System tick timer.

 Memory:

 32 kB on-chip flash programming memory.

 8 kB SRAM.

 In-Application Programming (IAP) and In-System Programming (ISP) support via

on-chip bootloader software.

 Digital peripherals:

 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors

and programmable open-drain mode.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 Four general purpose counter/timers with a total of one capture input and 10 match

outputs.

 Programmable windowed WatchDog Timer (WDT).

 Analog peripherals:

 10-bit ADC with input multiplexing among five pins.

 Serial interfaces:

 UART with fractional baud rate generation, internal FIFO, and RS-485 support.

 One SPI controller with SSP features and with FIFO and multi-protocol capabilities

(see Section 7.16).

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used

as a system clock.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from an external clock or the internal RC

oscillator.

 Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock (LPC1104 only).

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep and Deep-sleep modes.

 Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simple function

call.

 Two reduced power modes: Sleep and Deep-sleep modes.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

six of the functional pins.

 Power-On Reset (POR).

 Brownout detect with up to four separate thresholds for interrupt and forced reset.

 Unique device serial number for identification.

 Single 3.3 V power supply (1.8 V to 3.6 V).

 Available as WLCSP16 package.