128K X 8 BIT CMOS SRAM

General Description The LP621024D is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus str

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128K X 8 BIT CMOS SRAM

General Description The LP621024D-I is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus st

文件：192.22 Kbytes 页数：17 Pages

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联笙电子

128K X 8 BIT CMOS SRAM

General Description The LP621024D-T is a low operating current 1,048,576- bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

文件：184.5 Kbytes 页数：16 Pages

AMICC

联笙电子

128K X 8 BIT CMOS SRAM

General Description\nThe LP621024D  is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply.\nInputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structure Single +5V power supply\nAccess times: 55/70 ns (max.)\nCurrent:\n  Very low power version:  Operating:  70mA   (max.)\n                                   Standby:  25mA  (max.)\nFull static operation, no clock or refreshing required\nAll inputs and outputs are directly TTL-compatible\nCommon I/O us;

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