LP2998MRESLASHNOPB中文资料德州仪器数据手册PDF规格书

1 Features

1• AEC-Q100 Test Guidance with the following

results (SO PowerPAD-8):

– Device HBM ESD Classification Level H1C

– Junction Temperature Range –40°C to 125°C

• 1.35 V Minimum VDDQ

• Source and Sink Current

• Low Output Voltage Offset

• No External Resistors Required

• Linear Topology

• Suspend to Ram (STR) Functionality

• Low External Component Count

• Thermal Shutdown

2 Applications

• DDR1, DDR2, DDR3, and DDR3L Termination

Voltage

• Automotive Infotainment

• FPGA

• Industrial/Medical PC

• SSTL-18, SSTL-2, and SSTL-3 Termination

• HSTL Termination

3 Description

The LP2998 linear regulator is designed to meet

JEDEC SSTL-2 and JEDEC SSTL-18 specifications

for termination of DDR-SDRAM and DDR2 memory.

The device also supports DDR3 and DDR3L VTT bus

termination with VDDQ min of 1.35 V. The device

contains a high-speed operational amplifier to provide

excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A

continuous current and transient peaks up to 3 A in

the application as required for DDR-SDRAM

termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and

a VREF output as a reference for the chipset and

DIMMs.

An additional feature found on the LP2998 is an

active low shutdown (SD) pin that provides Suspend

To RAM (STR) functionality. When SD is pulled low

the VTT output will tri-state providing a high

impedance output, but, VREF will remain active. A power savings advantage can be obtained in this

mode through lower quiescent current.