LP2995中文资料DDR 终端稳压器数据手册TI规格书

描述 Description

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.

特性 Features

• Low Output Voltage Offset
• Works with +5v, +3.3v and 2.5v Rails
• Source and Sink Current
• Low External Component Count
• No External Resistors Required
• Linear Topology
• Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
• Low Cost and Easy to Use