LP1071中文资料飞思卡尔数据手册PDF规格书

Introduction

The LP1070 Family

Freescale Semiconductor’s 802.11 LP1070 family consists of high-performance, highly optimized PHY and MAC baseband Wireless LAN processors that fully implement the IEEE 802.11a, 802.11b and 802.11g PHY standards. These baseband processors are poised to revolutionize the Wireless LAN industry by setting new standards for power consumption, size, cost and performance.

The LP1070 family is based on Freescales proprietary Wireless Broadband Signal Processor™ (WBSP™), an innovative and revolutionary receiver architecture that significantly reduces size and power consumption while providing maximum flexibility to support multiple wireless standards with no additional overhead.

General Description

The high-performance LP1071 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC functionality with the industry’s smallest package and the lowest power consumption compared to any baseband processor in the market.

The LP1071 was designed to target embedded devices and small form factor SDIO WLAN devices. Its support for SDIO host interface combined with its ultra low power consumption and small size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that lets it interface with virtually any RF components in the market. It has been fully tested to interface with RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in selecting the most appropriate RF parts based on their application and form factor.

Feature Highlights

• Full compliance with 802.11a/b/g

• Ultra low power consumption, maximizing battery life and minimizing heat dissipation

• Ultra small package: 9.0 x 9.0 x 1.0 (max) mm

• Fully embedded ARM7TDMI® microprocessor for no load on the host processor, leading to maximum flexibility in supporting different host platforms

• Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications

• 802.11i support, including WPA and AES, for enhanced security

• Automatic power management to reduce power consumption

• On-chip ADC and DAC to reduce system BOM and save on board area

• On-Chip PLL for clock generation

• On-chip ROM/RAM eliminating the need for external MAC memory

• Direct memory access (DMA) to reduce CPU utilization

• High throughput achieved using DMA

• Support of SDIO host interface

• Serial EEPROM interface for initialization and device booting

• Eight General Purpose I/O (GPIO) pins for added flexibility

• UART interface to support diagnostic tools and general data transfer

• JTAG Interface for testing and debugging

• Hardware engines for WEP, TKIP and AES support for less processor load

• Supports Direct Conversion (Zero-IF) radio architecture, saving RF components thus reducing BOM cost and simplifying board layout

• Generic RF interface that lets it work with virtually an WLAN RF components. Currently fully tested with RF from Maxim and Airoha.

• Total Flexibility in meeting customer requirements by providing software-controlled trade-off between competing performance metrics.