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LMX1906PAP/EM中文资料德州仪器数据手册PDF规格书

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厂商型号

LMX1906PAP/EM

功能描述

LMX1906-SP Space Grade Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

丝印标识

LMX1906PAP/EM

封装外壳

HTQFP

文件大小

2.9657 Mbytes

页面数量

72

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-12-23 17:09:00

人工找货

LMX1906PAP/EM价格和库存,欢迎联系客服免费人工找货

LMX1906PAP/EM规格书详情

1 Features

• SMD #5962-23202

– Total ionizing dose 100 krad (ELDRS-free)

– Single event latch-up (SEL) immune up to 87

MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 87 MeV - cm2 /mg

• Clock buffer for 300-MHz to 15-GHz frequency

• Ultra-Low Noise

– Noise floor of –159 dBc/Hz at 6-GHz output

– 36-fs additive jitter (100 Hz to fCLK) at 6-GHz

output

– 5-fs additive jitter (100 Hz - 100 MHz)

• 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

• Support pin mode options to configure the device

without SPI

• LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

• 8 programmable output power levels

• Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5 ps

each at 12.8 GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

• SYNC feature to all divides and multiple devices

• 2.5-V operating voltage

• –55ºC to +125ºC operating temperature

2 Applications

• Radar imaging payload

• Communications payloads

• Command and data handling

• Data converter clocking

• Clock distribution/multiplication/division

3 Description

The LMX1906-SP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

solution for clocking data converters, especially when

sampling above 3 GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the mutlichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

供应商 型号 品牌 批号 封装 库存 备注 价格
NS
25+
SOP.16
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24+
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22+
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NS
25+
SOP16
4500
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23+
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2015+
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19889
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NS
00/98+
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1120
全新原装现货100真实自己公司
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