LMK61E08中文资料Ultra-low jitter programmable oscillator with internal EEPROM数据手册TI规格书

描述 Description

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

特性 Features

• Ultra-Low Noise, High Performance
• PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
• Flexible Output Format on LMK61E08
• LVDS up to 900 MHz
• Total Frequency Tolerance of ±25 ppm
• Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
• Other Features
• 3.3-V Operating Voltage
• 7-mm × 5-mm 6-Pin Package
• Default Frequency:
• 70.656 MHz