丝印：LK5C33216A；Package：VQFN；LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.6477 Mbytes 页数：99 Pages

TI

德州仪器

丝印：LK5C33216A-S1；Package：VQFN；LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.65279 Mbytes 页数：99 Pages

TI

德州仪器

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

文件：3.42385 Mbytes 页数：93 Pages

TI

德州仪器

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器

LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW

1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20

文件：3.77176 Mbytes 页数：94 Pages

TI

德州仪器