LMK3H0102数据手册TI中文资料规格书

描述 Description

LMK3H0102 是一款 2 输出 PCIe 第 1 代至第 6 代兼容无基准时钟发生器，支持展频时钟 (SSC)。该器件基于 TI 专有的体声波 (BAW) 技术，无需任何晶体或外部时钟基准即可提供 ±25ppm 时钟输出。该器件可以同时提供 2 个 SSC 时钟、2 个非 SSC 时钟，或者同时提供 1 个 SSC 时钟和 1 个非 SSC 时钟。该器件满足从第 1 代到第 6 代的完整 PCIe 合规性，包括具有或不具有 SSC、独立基准无展频 (SRNS) 和独立基准独立展频 (SRIS) 的通用时钟。

可通过 GPIO 引脚或 I 2C 接口轻松配置该器件。可以使用一个外部直流/直流转换器为该器件供电。有关电源滤波和通过直流/直流转换器供电的详细指南，请参阅 电源相关建议。

特性 Features

• Integrated BAW resonator, no need for external reference
• Flexible frequency generation:
• Two channel dividers: up to three unique output frequencies from 2.5 MHz to 400 MHz
• LVCMOS outputs supported up to 200 MHz: 1.8 V, 2.5 V, or 3.3 V
• Combination of AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS on OUT0 and OUT1 pins
• Additional LVCMOS output for generation of up to 5 LVCMOS clocks

• Total output frequency stability: ±25 ppm
• 2 functional modes: I 2C or preprogrammed OTP
• Fully configurable I 2C address

• Ambient temperature: –40 °C to 85 °C
• PCIe Gen 1 to Gen 6 compliant: Common Clock with or without SSC, SRNS, and SRIS
• Very low PCIe jitter
• PCIe Gen 3 Common Clock jitter: 140 fs maximum (PCIe limit is 1 ps)
• PCIe Gen 4 Common Clock jitter: 140 fs maximum (PCIe limit is 500 fs)
• PCIe Gen 5 Common Clock jitter: 45 fs maximum (PCIe limit is 150 fs)
• PCIe Gen 6 Common Clock jitter: 45 fs maximum (PCIe limit is 100 fs)

• Mixed SSC and non-SSC output modes supported, all PCIe Gen 1 to Gen 6 compliant
• 2x SSC outputs, 2x non-SSC outputs, or 1x SSC output and 1x non-SSC output

• Programmable SSC modulation depth
• Preprogrammed: –0.1%, –0.25%, –0.3%, and –0.5% down spread
• Register programmable: –0.1% to –3% down spread or ±0.05% to ±1.5% center spread

• VDD = VDDO = 1.8 V / 2.5 V / 3.3 V ± 5%
• As low as 60 mA current consumption when both outputs are LP-HCSL
• Internal LDOs with –93.1 dBc PSNR at 500 kHz switching noise for LP-HCSL outputs
• Start-up time: